The present invention relates to a vertical power semiconductor device (hereinafter referred to as “power device”) primarily made of a silicon carbide (SiC) semiconductor material and capable of voltage driving through an insulated gate.
Devices that handle a large amount of electric power, so-called power devices, have been conventionally manufactured by primarily using silicon semiconductors. Since a power device can have a large electric current capacity, it often has a structure in which electric current flows in the thickness direction (vertical direction) between the two principal planes of the chip. Among such conventional power devices is a vertical insulated gate field effect transistor. FIG. 9 is a cross-sectional view of a conventional representative vertical insulated gate field effect transistor (MOSFET).
The cross-sectional view shown in FIG. 8 is the basic structure of a well known device called a static induction transistor (hereinafter abbreviated as “SIT”). The SIT structure includes gates obtained by selectively burying p+ regions 54 in an n-type high-resistance (low-concentration) drift layer 53 deposited on an n+ semiconductor substrate 51. When a negative bias is applied to the gate with respect to a drain 56 provided on the underside of the semiconductor substrate 51, a depletion layer expands in a pinch-off region 52 provided between each pair of the p+ regions 54, which are the gates, and blocks the electric current path from the drain 56 through the pinch-off region 52 and an n+ source region 57 to a source 58. Such SIT devices are characterized by a monopolar structure in which electric current basically only flows through n-type regions, so that small on-resistance close to an ideal value is likely provided. Prototype devices have been reported having the SIT structure using SiC semiconductors with excellent characteristics as well as those using silicon semiconductors. However, the basic structure of the SIT device is in the conducting state when no bias is applied to the gate (normally-on). Therefore, when the gate drive circuit malfunctions due to noise or the like and hence no gate voltage is applied, the device remains conducting, possibly resulting in a serious failure, such as breakdown of the circuit in the worst case. Use of the SIT device requires caution in the gate bias conditions, which poses difficulty in using the SIT device.
The vertical MOSFET, an insulated gate-driven device, is frequently used as the power device described above. FIG. 9 shows a typical planar gate MOSFET in which gate insulating films 124 and gate electrodes 111, each having a flat shape, are formed on the principal plane of a semiconductor substrate (100+103). In FIG. 9, n+ surface regions 121 provided immediately under the gate insulating films 124 located on both sides of a p-well 113 in the substrate surface are not formed in many cases. When reduction in size of the unit pattern for lowering on-resistance of the power device narrows the region immediately under the gate insulating film 124 sandwiched between the p-wells 113 in adjacent unit patterns, the pinch-off resistance increases because a depletion layer expands when a bias is applied to a drain electrode 106. To prevent the pinch-off resistance and hence the on-resistance from increasing, the high-concentration n+ surface regions 121 are provided. The concentration (impurity concentration) is approximately 1×1018 cm−3 at the most, because higher concentrations prevent the depletion layer from expanding along the surface, resulting in reduction in blocking voltage. Reference numeral 111 denotes the gate electrode. Reference numeral 104 denotes an interlayer insulating film. Reference numeral 105 denotes an emitter electrode. Reference numeral 114 denotes an emitter region. Reference numeral 115 denotes a contact high-concentration p+ region.
In the vertical MOSFET, unlike the SIT shown in FIG. 8, the on-resistance of the element includes not only the resistance of the n-type semiconductor region (the high-resistance drift layer 103, in particular) but also the resistance in channel regions that are located immediately under the gate electrodes 111 and the gate insulating films 124, and formed in the surfaces of the p-well 113 sandwiched between the emitter regions 114 and the high-concentration n+ surface regions 121. The total resistance of the channel regions in the whole element decreases when the size of the unit pattern is reduced to increase the channel density, since the channel regions are arranged in parallel. Accordingly, to lower the on-resistance of the whole element, the unit pattern is preferably configured in such a way that the channel density is maximized.
The cross-sectional view of FIG. 10 shows a conventional trench gate MOSFET devised in such a way that more reduction in channel resistance through the size reduction described above is achieved than in the planar gate MOSFET. In the trench gate structure indicated by a gate electrode 223, a gate insulating film 224, and a trench 235, the trench 235 extends downward perpendicularly to the principal plane, so that the trench density along the surface can be easily increased. The trench gate structure (223, 224, and 235) therefore easily achieves a higher channel density than that in the planar gate structure shown in FIG. 9. Furthermore, in the trench gate structure, the fact that the pinch-off resistance in the region sandwiched between p-wells 225 structurally decreases makes the trench gate MOSFET more advantageous than the planar gate MOSFET from the viewpoint of the pinch-off resistance. Reference numeral 220 denotes an n+ semiconductor substrate. Reference numeral 222 denotes a high-resistance drift layer. Reference numeral 228 denotes an n+ emitter region. Reference numeral 226 denotes a p+ contact region. Reference numeral 230 denotes an interlayer insulating film. Reference numeral 227 denotes an emitter electrode.
However, in a silicon power device, since the channel density has already been almost maximized by making full use of the process technology of the trench gate structure and the LSI microprocessing technology, the semiconductor characteristics of the silicon power device have approached the limit determined by the material. To break through this material limit, there have been attempts to change the semiconductor material from silicon to any of those having broader band gaps, such as SiC and GaN. Since the maximum breakdown fields of these materials are larger by approximately one order of magnitude than that of silicon, it is expected that use of any of these materials for a power device lowers the resistance of the element to one hundredth or smaller. Prototypes of SiC-MOSFET devices and SiC-SIT devices having structures similar to those of silicon devices have been built and have shown excellent characteristics.
JP-A-2006-147789 and corresponding European Patent Publication EP 1,814,162 A1 describe a SiC-MOSFET in which the on-resistance is lowered by forming a structure including an n+ SiC substrate, an n-type high-resistance (low-concentration) drift layer stacked thereon, a high-concentration p-gate layer buried therein, and a MOS channel region further formed thereon, the MOS channel region being a low-concentration p-type deposition layer. It is necessary to selectively convert the p-type deposition layer into an n-type base region through ion implantation to form an electric current path. However, the n-type base region cannot be thick due to the practical limit of depth to which ions can be implanted (equal to the thickness of the p-type deposition layer), so that a high electric field is applied to the gate insulating film and hence the off-state voltage is not improved. To solve this problem, the above-referenced documents reported interposing a low-concentration n-type deposition layer between the low-concentration p-type deposition film and the high-concentration gate layer of a SiC MOSFET. The base region converted into the n-type through ion implantation is selectively formed in the low-concentration p-type deposition film so as to increase the thickness of the n-type deposition film between the high-concentration gate layer and the low-concentration p-type deposition film (channel region).
JP-A-2001-94097 discloses a MOSFET device as shown in the cross-sectional view of the semiconductor substrate of the MOSFET in FIG. 11. This device includes an n+ channel layer 305a deposited on the exposed surface of an n− epitaxial layer 302a stacked on an SiC-n+ substrate 1 and on part of the surfaces of p− base regions 303a and 303b, n+ source regions 304a and 304b formed in the surface portions of the p− base regions 303a and 303b, ion implanted p-type channel layers 305b, one of the channel layers sandwiched between the n+ source region 304a and the n-type channel layer 305a and the other sandwiched between the n+ source region 304b and the n-type channel layer 305a, and a gate electrode 308 formed above the channel layers 305b and the n-type channel layer 305a via a gate insulating film 307. This SiC semiconductor device not only has the MOSFET channel structure having the normally-off capability but also a capability to lower the on-resistance even when the depletion layer expands between the p− base regions 303a and 303b at the time of ON by increasing the concentration in the n-type channel layer 305a. 
As described above, a MOSFET made of a silicon carbide semiconductor is expected to have an excellent blocking voltage characteristic because the dielectric breakdown field of a silicon carbide semiconductor is higher than that of a silicon semiconductor by one order of magnitude. However, a SiO2 film is primarily used as the gate insulating film as in silicon semiconductor, that is, a large blocking voltage cannot be provided in many cases. Corners are formed on the gate insulating film and the electric field concentrates at the corners of the gate insulating film, so that an excessive electric field is applied, particularly in a trench MOSFET. An electric field normally applied in SiC therefore cannot be applied, so that only a much lower blocking voltage is provided. Accordingly, to avoid the problem of reduced blocking voltage due to dielectric breakdown of the gate insulating film in silicon carbide semiconductor, a planar gate MOSFET has been fabricated as a prototype in many cases.
Since a SiC semiconductor has lower channel mobility in a MOSFET than a silicon semiconductor, a high-density channel structure is more desirable to lower the channel resistance than in silicon semiconductor. However, a sufficiently high-density channel structure is not always provided since a SiC semiconductor needs to employ a planar gate MOSFET as described above, which suffers from a low level of channel size reduction. Since a SIT uses no gate insulating film, it does not have the problem of insulating film breakdown described above. However, a SIT is a so-called normally-on device, that is, it has source-drain continuity in the no-bias state in which no voltage is applied to the gate. This becomes a problem when a SIT is actually applied to a circuit, and hence a SIT is regarded as a hard-to-use device. In a practical circuit, when a problem occurs in a gate circuit and no voltage can be applied to the gate, a so-called normally-off device is preferable from the viewpoint of safety because a normally-off power device having such a defective gate automatically blocks electric current.
As a method to eliminate the normally-on device phenomenon from a power device having the SIT structure, there has been proposed a complex device structure shown in an equivalent circuit in FIG. 2. This device has a structure in which a SIT 16 and a MOSFET 15, which is a low blocking voltage normally-off device, are serially cascaded. When an off-state signal is applied to the gate 18 of the MOSFET 15, the MOSFET 15 becomes blocked, so that the potential at the source region of the SIT 16 increases. A negative bias is therefore applied to the gate of the SIT 16, so that the SIT 16 is also turned off. The device having such a configuration is a normally-off device without the normally-on device phenomenon. This configuration, however, results in a large on-resistance device in which the MOSFET 15 is added to the SIT 16, which means that the advantage of a SiC semiconductor device, namely small on-resistance with a small area, is lost.
In view of the points described above, it would be preferable to provide an insulated gate silicon carbide semiconductor device and a method for manufacturing the same, wherein the semiconductor device has small on-resistance, the advantage of the static induction transistor structure is fully used, and the advantage of the field effect transistor structure characterized by the normally-off operation is obtained, in a structure obtained by combining the static induction transistor structure with the insulated gate field effect transistor structure.